In the following we describe some known methods used for the channel delay profile estimation in CDMA receivers. These methods can be divided in two different groups depending on the particular architecture employed. We can consider methods based on the Code Delayed Architecture (CDA) or methods based on the Data Delayed Architecture (DDA).
In a CDA delay profile estimator one replica of the PN sequence is generated at the receiver and directly correlated with the received data. During the subsequent correlation operations the phase of the PN sequence is cyclically changed in order to scan other positions (i.e. delays) of the receiving search window.
In a DDA delay profile estimator the phase (i.e. delay) of the received data is cyclically changed whereas the phase of the PN sequence is kept fixed. The shift of the received data is usually obtained, by storing the received signal samples in a delay line and cyclically taking the samples, for the correlation operation, from the different positions of the delay line.
In the description of the known methods the various signals are expressed in terms of complex envelope so that each signal is represented by the two components: in-phase (I) and in-quadrature (Q). The information sequence generated by the transmitter is represented with u(n) where n is the discrete time index related to the information symbol period Ts u(n)=u(n·Ts)n=0,1,2 . . .
The PN code sequence S(k) is expressed asS(k)=S(k·TC)=SI(k)+j·SQ(k)k=0,1,2, . . .where k is the discrete time index related to the chip period TC. The PN sequence is periodic with a period of SF chips (SF is the Spreading Factor) and a different sequence is assigned to each user in order to minimise the cross-interference among the users sharing the same channelS(k)=S(k+SF)∀k≧0
The information sequence u(n) is spread by means of the multiplication of each information symbol with the PN code sequence S(k), made by SF subsequent chips, as followsx(k)=xI(k)+j·xQ(k)=u(kdivSF)·S(k)
As a consequence the chip period TC is SF times smaller than the symbol period TS and, after the spreading operation, the signal bandwidth of the information sequence is increased by a factor SP. The discrete time index n of the information sequence is expressed as a function of the discrete time index k of the chip sequence by means of the following expressionn=kdivSFwhere k div SP is the integer part of the quotient between k and SF.
The signal x(k) is then filtered and transmitted over the propagation channel. In the particular case of a propagation channel with only one direct path between the transmitter and the receiver, the base-band signal arriving at the input of the Rake receiver, from the receiver front-end, is denoted as y(k) and it can be expressed as followsy(k)=x(k)·c(k)+n(k)=u(kdivSF)·S(k)·c(k)+n(k)where c(k)=cI(k)+j·cQ(k) represents the distortion introduced by the propagation channel (due to fast fading and Doppler effect) and n(k)=nI(k)+j·nQ(k) represents the effect of thermal noise plus interference.
The channel delay profile is indicated with h(1)=hI(1)+j·hQ(1) where 1 is the variable spanning over the channel delay spread. We assume that the time spreading of the channel is limited to H chips before the strongest received signal replica and T chips after that replica. As a consequence the variable 1 spans in the range−H≦1≦T where the value 1=0 corresponds to the time position of the strongest signal replica, which is usually taken as a reference for the synchronism of the receiver. Therefore, the receiving search window, where the Rake receiver is able to capture the energy of the received multi-path components, has a length of H+T+1 chips.Finally we define the channel delay profile energy DP(1) as followsDP(1)=hI2(1)+hQ2(1)Now we describe the following methods for the channel profile estimation:                Serial correlator (CDA)        Bank of correlators (CDA)        Serial correlator (DDA)        Matched filter (DDA)        
The first method for the channel profile estimation is the serial correlator based on a CDA, whose structure is shown in FIG. 1.
The received signal y(k) is multiplied with the complex conjugate of the PN sequence S*(k−1) and the result is accumulated over an integration window of NC subsequent chips where, for example, NC can be equal to SP. After the integration, the energy of the channel profile is computed by taking the squared sum of the two signal components. The channel profile is computed according to the following equation
      h    ⁡          (      1      )        =            ∑              i        =        k                    k        +        NC        -        1              ⁢                  y        ⁡                  (          i          )                    ·                        S          *                ⁡                  (                      i            -            1                    )                    The profile energy is then given byDP(1)={Re[h(1)]}2+{Im[h(1)]}2 
Each value of 1 (−H≦1≦T) corresponds to one particular delay of the code sequence and to one point of the channel profile. The computation of one point of the delay profile requires a time interval of NC chips and, in general, for a delay profile of H+T+1 points the time required for the profile computation is equal totprofile=(H+T+1)·NC[chips]
In order to reduce the time required for the profile computation it is possible to use a bank of serial correlators where each correlator is fed with a different replica of the PN code sequence. For example by using H+T+1 correlators the time required for the profile computation reduces to NC chips as all points of the profile are computed in parallel.tprofile=NC[chips]
The block diagram of a bank of serial correlators based on the CDA solution is shown in FIG. 2. The different replicas S*(k+H), S*(k+H−1) . . . S*(k−T) of the PN code sequence are obtained by using a single code generator that writes the code values in a memory buffer. The different replicas of the PN code can be read, simultaneously, from the different positions of the memory buffer 2 as shown in FIG. 3.
The serial correlator DDA represents a dual solution with respect to the serial correlator CDA. In the DDA solution the phase of the PN code is kept fixed while the phase of the received data is changed. This is obtained by storing the received samples in a delay line 4 and cyclically taking the samples for the correlation operation from the different positions of the delay line. The block diagram of the serial correlator DDA is shown in FIG. 4.
The channel profile is computed according to the following equation
      h    ⁡          (      1      )        =            ∑              i        =        k                    k        +        NC        -        1              ⁢                  y        ⁡                  (                      i            +            1                    )                    ·                        S          *                ⁡                  (          i          )                    while the profile energy is given byDP(1)={Re[h(1)]}2+{Im[h(1)]}2 
The time required for the computation of one point of the profile is the same of the CDA solution and it is equal to NC chips. As a consequence the time required for the computation of the complete profile over H+T+1 points is equal totprofile=(H+T+1)·NC[chips]
By using a matched filter it is possible to reduce the time required by the DDA solution for the channel delay profile computation. A matched filter is a filter whose frequency response is designed to exactly match the frequency spectrum of the input signal. In CDMA systems the matched filter is tuned to match a code sequence that is expected to be present within the digital samples entering in the receiver. For example, in the case of the UMTS system, a channel suitable for the uplink channel delay profile estimation is the DPCCH (Dedicated Physical Control Channel).
The matched filter is the dual solution with respect to the bank of serial correlators for the CDA. The filter is matched to the PN sequence and therefore the filter coefficients fcoeff(j) are obtained by means of the following expressionfcoeff(j)=S*(NC−j)1≦j≦NC 
The block diagram of the matched filter is shown in FIG. 5.
The matched filter detects the presence of the PN code sequence in the input data stream; the output of the matched filter can be viewed as a score value indicating the match with the code sequence. A high score value represents a good correlation of the input data with the PN code sequence.
The matched filter output is computed according to the following equation
      h    ⁡          (      1      )        =            ∑              i        =        k                    k        +        NC        -        1              ⁢                  y        ⁡                  (                      i            +            1                    )                    ·                        S          *                ⁡                  (                      i            -            k                    )                    
The profile energy is given byDP(1)={Re[h(1)]}2+{Im[h(1)]}2 The time required by the matched filter to compute the channel delay profile is equal to the search window length, that is H+T+1 chips, plus (NC−1) chips necessary to fill the filter delay line with the incoming samplestprofile=H+T+1+(NC−1)[chips]The matched filter (DDA) and the bank of correlators (CDA) offer faster path detection than other solutions but they present high complexity and power consumption.
The theory underlying the operations performed by a bank of correlators (CDA) or a matched filter (DDA) for the computation of the channel delay profile in a spread spectrum receiver is illustrated in R. L. Pickholtz, D. L. Shilling, L. B. Milstein, “Theory of Spread Spectrum Communications—A Tutorial”, IEEE Transactions and Communications, Vol. COM-30, No. 5, May 1982.
The problem of reducing the complexity of the architecture of a matched filter is addressed in U.S. Pat. No. 5,715,276. This patent relates to a matched filter (DDA), for use as part of a spread spectrum receiver, wherein the filter length is broken into two halves of length N/2 each, where N is the number of taps on the matched filter.
Although the matched filter described in U.S. Pat. No. 5,715,276 requires fewer logic gates, compared to a classical matched filter the overall hardware implementation of the filter is however relevant.
It is likewise well known that the architecture of a Rake receiver always incorporates a memory buffer, for temporarily storing input data streams (DDA), or the locally generated PN code (CDA).
The architecture disclosed in WO 00/25437 is an example of a Rake receiver (DDA) architecture provided with an input memory buffer, implemented as a dual-port RAM. The I/Q sample pairs at the input of the Rake receiver are stored in the RAM memory through a first port, while a second port is used for accessing the same memory in read mode.
Another prior art Rake receiver architecture (DDA), incorporating an input memory buffer, is disclosed in H. Lasse, N. Jari, “A Flexible Rake receiver Architecture for WCDMA Mobile Terminals”, Third IEEE Signal Processing Workshop on Signal Processing Advances in Wireless Communications, Taoyuan, Taiwan, Mar. 20-23, 2001.
Such architecture incorporates an input memory buffer, used for storing the I/Q sample pairs at the input of the Rake receiver, implemented as an input stream buffer which can be comprehended as a time-sliding window divided into three parts: a write window allowing writing to the buffer, a pre-window and a post-window allowing read accesses without overlapping with the write window. The read and write accesses are interleaved in time in order to avoid the need of concurrent memory accesses. A correlator engine reads the multipath samples from the stream buffer and performs the despreading of the multipath components sequentially.
Another prior art Rake receiver architecture (CDA), incorporating an input memory buffer for the different phases of the PN code sequence, is disclosed in U. Grob, A. L. Welti, E. Zollinger, R Kung and H. Kauffman “Microcellular Direct-Sequence Spread-Spectrum Radio System Using N-Path RAKE Receiver”, IEEE Journal on Selected Areas in Communications, Vol. 8, June 1990.
The Applicant has tackled the problem of further reducing the overall complexity and silicon requirement of a channel delay profile estimation unit in a Rake receiver.
The Applicant observes that, in a Rake receiver, a RAM buffer is always required, independently on the choice of the receiver architecture. The RAM buffer is used to store the data arriving from the receiver front-end, in the case of a DDA architecture, or the data arriving from the Code Generator Circuit, in the case of a CDA architecture.
The Applicant has observed that, in the previously described technique making use of a matched filter (DDA), the delay line of the matched filter duplicates in part the function of the RAM buffer for storing the data arriving from the receiver front-end. As a matter of fact, both the delay line and the RAM buffer store the same data.
In a similar way the Applicant has observed that, in the previously described technique making use of a bank of correlators (CDA), the delay line, necessary for the generation of the different phases of the PN sequence, duplicates in part the function of the Rake receiver RAM buffer for storing the different PN code replicas. As a matter of fact, both the delay line and the RAM buffer store the same data.
In view of the above, it is an object of the invention to provide a method and a device for the estimation of the channel delay profile in a digital communication receiver, allowing to reduce the hardware complexity of the Rake receiver, reducing consequently the silicon area of the chip on which the system is integrated.